1. Field of the Invention
The present invention generally relates to the fabrication of integrated circuits, and, more particularly, to the manufacture of field effect transistors having a doped gate electrode, such as a doped polysilicon gate electrode, wherein a dopant concentration is controllable independently from a dopant concentration in the drain and source regions.
2. Description of the Related Art
The fabrication of integrated circuits requires the formation of a huge number of circuit elements on a given chip area according to a specified circuit layout. Generally, a plurality of process technologies are currently practiced, wherein, for logic circuitry, such as microprocessors, storage chips and the like, CMOS technology is currently the most promising approach due to the superior characteristics in view of operational speed and/or power consumption. In this technology, millions of complementary transistors, i.e., N-channel transistors and P-channel transistors, are formed on an appropriate substrate, wherein the ongoing demand for improved transistor performance has now rendered so-called SOI devices a preferred circuit architecture for highly advanced CMOS devices. SOI devices are manufactured in and on a relatively thin semiconductor layer, typically silicon (silicon on oxide), which in turn is formed on an insulating layer. By means of corresponding isolation structures completely enclosing a circuit element, complete electrical insulation from other circuit elements is achieved, thereby providing a plurality of advantages that may not readily be accomplished by conventional CMOS devices manufactured on bulk semiconductor substrates. Irrespective of the circuit architecture used, a typical MOS transistor comprises PN junction regions that are separated from each other by a channel region, which is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The dimension of the channel region corresponding to the distance between the two PN junction regions, which are also referred to as drain regions and source regions, is denoted as channel length and represents the dominant design characteristic of the MOS transistor. By reducing the channel length of the transistor, not only the transistor size but also the functional behavior thereof may be specifically designed so as to obtain a desired transistor performance. Presently, a gate length of approximately 0.1 μm and significantly less may be encountered in advanced CMOS devices with corresponding clock frequencies of 2000 MHz and more. Although the continuous size reduction of transistor elements has provided significant advantages in view of performance and/or power consumption, a plurality of issues has to be addressed so as to not unduly offset some of the advantages that are offered by the reduced dimensions of the circuit elements. Especially, the fabrication of the circuit components having the critical dimensions, such as the gate electrode of the transistor element substantially determining the channel length, requires huge efforts so as to reliably and reproducibly form these tiny circuit components. For instance, it is an extremely complex process to form gate electrodes having a gate length that is well below the wavelength of the UV radiation used to transfer a layout image from a reticle to a resist layer formed on the substrate.
A further difficulty arises from the fact that the PN junctions are defined by dopant profiles that are, at least partially, created by ion implantation and subsequent anneal cycles. Since, typically, reduced feature sizes require higher dopant concentrations to compensate for the reduced conductivity owing to reduced cross-sectional areas, complex implantation cycles are required, wherein the vertical and lateral dopant profile has to be precisely controlled so as to achieve the desired transistor performance. Since the dopants implanted are subjected to diffusion upon elevated temperatures of the device during the manufacturing processes, very strict requirements have to be met with respect to a thermal budget that describes the diffusivity of the dopants over time. For instance, advanced transistor elements require extreme high doping levels in the drain and source regions, which are in conventional process technologies also supplied to the gate electrode acting as an implantation mask during the implant cycles, wherein, particularly for P-channel transistors that may be doped with boron, a severe boron diffusion into the gate insulation layer may take place, thereby causing severe reliability constraints for the device.
Other problems result from the fact that a reduced transistor gate length also requires extremely shallow PN junctions in order to maintain the required controllability of the channel conductivity. For SOI devices, therefore, the thickness of the silicon layer has to be correspondingly reduced, which, in turn, may result in an increased contact resistance to the drain and source regions owing to a reduced surface area connecting the highly doped semiconductor regions with a metal silicide region formed in drain and source areas.
With reference to FIGS. 1a-1d, a typical conventional process flow for forming an advanced SOI MOS transistor will now be described to discuss some of the problems involved in extreme device scaling in more detail. In FIG. 1a, a transistor 100 comprises a substrate 101 having formed thereon an insulating layer 102, which is frequently referred to as buried oxide, and a crystalline silicon layer 104. A thickness of the silicon layer 104 is selected in conformity with the overall device dimensions and is especially adapted to the length of a gate electrode 105, which is formed above the silicon layer 104 and is separated therefrom by a gate insulation layer 106. The gate electrode 105 is typically comprised of polysilicon and the gate insulation layer 106 may be comprised of silicon dioxide, silicon oxynitride, and the like. An isolation structure 103 substantially defines the dimensions of the transistor 100 and electrically insulates the transistor 100 from neighboring circuit elements. Sidewall spacers 107 are formed on the sidewalls of the gate electrode 105, and drain and source regions 108, having a specified lateral dopant profile, are formed within the silicon layer 104.
A typical process flow for forming the transistor 100 as depicted in FIG. 1a may include the following processes. The substrate 101 including the insulating layer 102 and the silicon layer 104 may be obtained from a corresponding substrate manufacturer with the required thickness of the silicon layer 104, or the thickness may be adapted by correspondingly polishing the substrate 101. In other cases, the substrate 101 including the layers 102 and 104 may be manufactured by well-known wafer-bond techniques. Thereafter, the isolation structure 103 is formed using well-established photolithography, etch, deposition and polishing techniques that are well known in the art. Thereafter, a thin dielectric layer having the required characteristics for the gate insulation layer 106 may be formed by, for instance, advanced oxidation and/or deposition processes. A polysilicon layer is then formed on the thin dielectric layer and this layer stack is then patterned by advanced photolithography and subsequent anisotropic etch processes to obtain the gate electrode 105 and the gate insulation layer 106 having the required gate length, i.e., the horizontal extension in FIG. 1a. Next, a first ion implantation sequence may be carried out so as to form extensions of the dopant profile for the drain and source regions 108, wherein the polysilicon gate electrode 105 acts as an implantation mask. Thereafter, the sidewall spacers 107 may be formed, depending on the process regime two or more spacers may be formed sequentially, and further ion implantation cycles are carried out so as to introduce the finally required dopant concentration into the drain and source regions 108. Again, the same dopant dose is also provided to the gate electrode 105. Thereafter, anneal cycles are performed so as to activate dopants and to re-crystallize, at least partially, those portions of the drain and source regions 108 that are damaged by the previous implantation sequences. For manufacturing P-channel transistors, boron is frequently used as the dopant for forming the drain and source regions 108, which exhibits a high diffusivity. Therefore, boron penetration into the gate insulation layer 106 during the implantation and the subsequent anneal cycles may take place and may reduce the reliability of the gate insulation layer 106, i.e., the long term resistance against electrical breakdown, may significantly drop. For extremely high boron doses, even the dopant concentration of the channel region formed between the drain and source regions 108 may be negatively influenced.
FIG. 1b schematically shows the transistor 100 according to one conventional approach that results in further issues with respect to device scaling. In FIG. 1b, a metal silicide region 109 is formed in the gate electrode 105 and corresponding metal silicide regions 110 are formed in the drain and source regions 108. The metal silicide regions 109 and 110 may be comprised of, for instance, cobalt silicide, which exhibits a significantly lower resistivity than silicon even when doped with the extremely high concentrations of advanced MOS transistors. Hence, it would be desirable for the metal silicide region 109 to occupy as much space as possible in the gate electrode 105 so as to efficiently reduce the resistivity thereof. The metal silicide regions 109 and 110 are formed in a common silicidation process, for instance involving the deposition of a refractory metal layer, a first anneal cycle so as to form cobalt monosilicide, a selective removal of non-reacted cobalt and a second anneal cycle so as to convert cobalt monosilicide into a low-ohmic cobalt disilicide. The demand for a large thickness of the metal silicide region 109 results in a complete consumption of the vertical extension of the drain and source regions 108, which, on the other hand, leads to an increased contact resistance to the drain and source regions 108 as the current flowing through the drain and source regions 108 may now enter the silicide region 110 through the lateral interface only, since the horizontal bottom interface of the metal silicide region 110 is no longer available for the charge carrier transport. As a consequence, frequently, an alternative approach will be employed, as is explained with reference to FIG. 1c. 
FIG. 1c schematically shows the transistor 100 prior to the formation of metal silicide regions. In FIG. 1c, silicon regions 111 are formed on the drain and source regions 108 and on the gate electrode 105 by selective epitaxial growth. Typically, the silicon regions 111 may then be grown after a first implantation for forming extensions of the drain and the source regions 108. Depending on the process requirements, the silicon regions 111 may be grown prior to or after the final implantation cycle for forming the drain and source regions 108.
FIG. 1d schematically shows the transistor 100 after the formation of the silicide regions 109 and 110 in the enlarged gate electrode 105 and the drain and source regions 108. As is shown, the silicidation process may now be controlled in such a manner that the metal silicide region 110 reaches into the drain and source regions 108 but, nevertheless, does not completely consume the silicon, thereby providing an increased interface for charge carrier transport to the channel region. Although this conventional transistor architecture may avoid some of the problems as discussed with reference to FIG. 1b, the ongoing device scaling may nevertheless bring about limitations of the physical gate length caused by conventional photolithography as the lithography and the subsequent anisotropic etch process substantially determine the gate length and, thus, the potentiality for transistor scaling. Moreover, as pointed out with reference to FIG. 1a, the dopant concentration in the gate electrode 105 is directly coupled with the dopant concentration provided in the source and drain regions 108, wherein this dopant concentration may be tailored to create a minimal contact and sheet resistance in these regions. However, especially for the highly diffusive boron of P-channel transistors, the gate dopant concentration must be thoroughly controlled to minimize dopant penetration of the gate insulation layer 106 and of the underlying channel region, leading to a conflict in selecting the implant parameters used to generate the drain/source dopant profiles.
In view of the problems identified, there still exists a need for an improved technique that enables the further scaling of the gate length substantially without compromising transistor performance, especially the performance of P-channel transistors.